1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit (IC) fabrication technology and, more particularly, to a method of forming a pad and a fuse in a semiconductor IC device.
2. Description of the Related Art
Semiconductor IC devices have metal pads, also referred to as bonding pads, etc., formed underneath and exposed to their exterior surfaces. The metal pads allow electrical access to and from internal device circuitry. In addition, most semiconductor IC devices, such as memory chips, have metal fuses formed underneath and exposed to their exterior surfaces. When there is a defect cell in the device, the metal fuses are used to replace the defect cell by using a spare cell.
FIGS. 1A and 1B show, in cross-sectional views, a conventional method of forming a pad and a fuse in a semiconductor device.
Referring to FIG. 1A, a copper layer 10 is formed in a dielectric layer 11 and connected to an underlying layer 12 such as metal lines. The copper layer 10 is covered with an insulating layer 13 in a fuse region 14 and exposed in a pad region 15. An aluminum pad 16 is formed on and connected to the exposed copper layer 10 in the pad region 15. Then, a passivation layer 17 is deposited on both the insulating layer 13 and the aluminum pad 16.
Referring to FIG. 1B, a suitable photoresist pattern 18 is formed on the passivation layer 17 and used as an etch mask for opening the aluminum pad 16. That is, in order to open the aluminum pad 16, the passivation layer 17 on the aluminum pad 16 is etched through the photoresist pattern 18.
The passivation layer 17 is traditionally made of silicon nitride, which may cause unfavorably scattered reflection of a laser beam when laser cutting is performed to the copper layer 10 in the fuse region 14. Therefore, a part of the passivation layer 17 in the fuse region 14 should be also etched to leave only the insulating layer 13 made of silicon oxide.
In the pad region 15, the passivation layer 17 is typically over-etched to obtain a reliable process margin. For example, when the passivation layer 17 is etched to a first thickness T1 in the pad region 15, the aluminum pad 16 is also partially etched to a second thickness T2. During such over-etching process, in the fuse region 14 both the passivation layer 17 and the insulating layer 13 are often etched together to a third thickness T3.
As a result, the copper layer 10 in the fuse region 14 may be exposed to the outside. In general, copper is very susceptible to contamination and may act as a pollution source due to high diffusible property. So the exposed copper layer 10 may become causes of drops in yield and reliability of the devices.